AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

ID 683185
Date 6/09/2020
Public

1.4. Hardware Checkout Methodology

The following section describes the test objectives, procedure, and the passing criteria. The test covers the following areas:
  • Receiver data link layer
  • Receiver transport layer
  • Deterministic Latency (Subclass 1)

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