Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 4/01/2024
Document Table of Contents Power-Aware Memory Balancing

Power-aware memory balancing chooses the best configuration for a memory implementation and provides optimal power saving by determining the required number of memory blocks, decoder, and multiplexer circuits. When the design does not specify target-embedded memory blocks for the design’s memory functions, the power-aware balancer automatically selects them during memory implementation.

The Compiler includes this optimization technique when the Power Optimization During Synthesis logic option is set to Extra effort.

There is a trade-off between power saved by accessing fewer memories and power consumed by the extra decoder and multiplexor logic. The Quartus® Prime software automatically balances the power savings against the costs to choose the lowest power configuration for each logical RAM. The benchmark data shows that the power-driven synthesis can reduce memory power consumption by as much as 60% in Stratix® devices.

You can also set the MAXIMUM_DEPTH parameter manually to configure the memory for low power optimization. This technique is the same as the power-aware memory balancer, but it is manual rather than automatic like the Extra effort setting in the Power optimization list. The MAXIMUM_DEPTH parameter always takes precedence over the Optimize Power for Synthesis options for power optimization on memory optimization. You can set the MAXIMUM_DEPTH parameter for memory modules manually in the Intel® FPGA IP instantiation or in the IP Catalog.