Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 4/01/2024
Document Table of Contents

2.4.7. DDR Memory Controller Settings

The External Memory Interfaces Arria® 10 FPGA IP provides low power mode settings. These settings put DDR memory in power saving mode when the controller is idle, providing power savings on external memory DDR. The ​Enable Auto Power-Down​ and Auto Power-Down Cycles​ settings enable this capability.

Low Power Mode Settings

  • Enable Auto Power-Down—directs the controller to place the memory device in power-down mode after a specific number of idle controller clock cycles. You can configure the idle wait time. All ranks must be idle to enter auto power-down.
  • Auto Power-Down Cycles—specifies the number of cycles the controller must be IDLE before entering the power down state. You determine the number based on the traffic pattern. If the number is too small, the control enters power down too frequently, affecting efficiency. The Arria® 10 device family supports from 1 to 65534 cycles.
Figure 38.  Arria® 10 EMIF Controller Parameters