Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 4/01/2024
Document Table of Contents

2.4.5. Dynamically Controlled On-Chip Terminations (OCT)

Dynamic OCT enables series termination (RS) and parallel termination (RT) to dynamically turn on/off during the data transfer. This feature is especially useful in FPGAs with external memory interfaces, such as interfacing with DDR memories.

Dynamic OCT eliminates the constant DC power that parallel termination consumes when transmitting data, reducing power consumption when compared to conventional termination. Parallel termination is extremely useful for applications that interface with external memories where I/O standards, such as HSTL and SSTL, are used. Parallel termination supports dynamic OCT, which is useful for bidirectional interfaces.

For more information about dynamic OCT in specific devices, refer to the Stratix® 10 General Purpose I/O User Guide or the Arria® 10 Core Fabric and General Purpose I/O Handbook .

Example: Power Saving for a DDR3 Interface with OCT

The static current consumed by parallel OCT is equal to the VCCIO voltage divided by 100 W. For DDR3 interfaces with SSTL-15, the static current per pin is:

Therefore, the static power is:

For an interface with 72 DQ and 18 DQS pins, the static power is:

Dynamic parallel OCT disables parallel termination during write operations, so if writing occurs 50% of the time, the power saved by dynamic parallel OCT is:

For more information about dynamic OCT in Stratix® IV devices, refer to the chapter in the Stratix® IV Device Handbook.