Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 4/01/2024
Document Table of Contents Generating Signal Activity Data for Power Analysis

To generate and use simulation signal activity data for power analysis:

  1. To run full compilation on your design, click Processing > Start Compilation.
  2. To specify settings for simulation output, click Assignments > Settings > EDA Tool Settings > Simulation. Select your simulator in Tool name and the Format for output netlist and Output directory.
    Figure 8. EDA Tool Settings for Simulation

  3. Turn on Map illegal HDL characters. This setting directs the EDA Netlist Writer to map illegal characters for VHDL or Verilog HDL, and results in more accurate data for power analysis.
  4. Click the Power Analyzer Settings page.
  5. For Stratix® 10 designs, to generate a Standard Delay Output (.sdo) file that includes back-annotation of delays for power analysis, refer to Generating Standard Delay Output for Power Analysis.
  6. Under Input file, turn on Use input files to initialize toggle rates and static probabilities during power analysis.
    Figure 9. Specifying Power Analysis Input Files
  7. To specify a .vcd for power analysis, click Add and specify the File name, Entity, and Simulation period for the .vcd, and click OK.
  8. To enable glitch filtering during power analysis with the .vcd you generate, turn on Perform glitch filtering on VCD files.
  9. To run the power analysis, click Start on the Power Analysis step in the Compilation Dashboard. View the toggle rates in the power analysis results.
Note: To improve accuracy of power analysis, the Quartus® Prime EDA Netlist writer can generate a Standard Delay Output (.sdo) file that includes back-annotation of delays for a design's netlist for use during simulation in QuestaSim*. Although the .sdo only contains delay estimates and imprecise timing information, including the .sdo in simulation results in a more accurate output .vcd for power analysis. The EDA Netlist Writer currently supports .sdo file generation only for Verilog .vo simulation in the QuestaSim* simulator (not ModelSim* - Intel® FPGA Edition) for Stratix® 10 designs. The EDA Netlist Writer does not currently support .sdo file generation for any other simulator or device family.