AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel Stratix 10 Devices

ID 683172
Date 12/18/2017
Public

1.3.4. Deterministic Latency (Subclass 1)

The figure below shows the block diagram of deterministic latency test setup. A SYSREF generator in the FPGA provides a periodic SYSREF pulse for both the AD9625 and JESD204B IP Core. The SYSREF generator is running in the link clock domain and the period of SYSREF pulse is configured to the desired multiframe size. The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.

Figure 4. Deterministic Latency Test Setup Block Diagram

The deterministic latency measurement block checks deterministic latency by measuring the number of link clock counts between the start of de-assertion of SYNC~ to the first user data output.

Figure 5. Deterministic Latency Measurement Timing Diagram

With the setup above, four test cases were defined to prove deterministic latency. The JESD204B IP Core does continuous SYSREF detection. The SYSREF continuous mode is enabled on the AD9625 for this deterministic latency measurement.

Table 5.  Deterministic Latency Test Cases
Test Case Objective Description Passing Criteria
DL.1

Check the FPGA SYSREF single detection.

Check that the FPGA detects the first rising edge of SYSREF pulse.

Read the status of sysref_singledet (bit[2]) identifier in syncn_sysref_ctrl register at address 0x54.

Read the status of csr_sysref_lmfc_ err (bit[1]) identifier in the rx_err0 register at address 0x60.

The value of sysref_singledet identifier should be zero.

The value of csr_sysref_lmfc_err identifier should be zero.

DL.2 Check the SYSREF capture. Check that FPGA and ADC capture SYSREF correctly and restart the LMF counter. Both FPGA and ADC are also repetitively reset.

Read the value of rbd_count (bit[10:3]) identifier in rx_status0 register at address 0x80.

If the SYSREF is captured correctly and the LMF counter restarts, for every reset, the rbd_count value should only drift within 1-2 link clocks due to word alignment.
DL.3 Check the latency from start of SYNC~ deassertion to first user data output. Check that the latency is fixed for every FPGA and ADC reset and power cycle.

Record the number of link clocks count from the start of SYNC~ deassertion to the first user data output, which is the assertion of jesd204_rx_link_valid signal. The deterministic latency measurement block in Figure 4 has a counter to measure the link clock count.

Consistent latency from the start of SYNC~ deassertion to the assertion of jesd204_rx_link_valid signal.
DL.4 Check the data latency during user data phase. Check that the data latency is fixed during user data phase.

Observe the ramp pattern from the Signal Tap Logic Analyzer.

The ramp pattern should be in perfect shape with no distortion.

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