AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel Stratix 10 Devices

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ID 683172
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices
1. Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization (ILA)
1. Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices

1.3. Hardware Checkout Methodology

The following section describes the test objectives, procedure, and the passing criteria. The test covers the following areas:

  • Receiver data link layer
  • Receiver transport layer
  • Descrambling
  • Deterministic latency (Subclass 1)

Section Content
Receiver Data Link Layer
Receiver Transport Layer
Descrambling
Deterministic Latency (Subclass 1)

Level Two Title