AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel Stratix 10 Devices

ID 683172
Date 12/18/2017
Public

1.3.2. Receiver Transport Layer

To check the data integrity of the payload data stream through the JESD204B receiver IP Core and transport layer, the ADC is configured to output PRBS-23 and Ramp test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP Core. The PRBS checker/Ramp checker in the FPGA fabric checks data integrity for one minute.

This figure shows the conceptual test setup for data integrity checking.

Figure 3. Data Integrity Check Using PRBS/Ramp Checker
Table 3.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria

TL.1

Check the transport layer mapping using Ramp test pattern.

The following signals in altera_jesd204_transport_rx_top.sv are tapped:

  • jesd204_rx_data_valid

The following signals in jesd204b_ed.sv are tapped:

  • data_error
  • jesd204_rx_int

The rxframe_clk is used as the sampling clock for the Signal Tap.

The data_error signal indicates a pass or fail for the PRBS checker.

  • The jesd204_rx_data_valid signal is asserted.
  • The data_error and jesd204_rx_int signals are deasserted.

TL.2

Check the transport layer mapping using PRBS-23 test pattern.

The following signals in altera_jesd204_transport_rx_top.sv are tapped:

  • jesd204_rx_data_valid

The following signals in jesd204b_ed.sv are tapped:

  • data_error
  • jesd204_rx_int

The rxframe_clk is used as the sampling clock for the Signal Tap.

The data_error signal indicates a pass or fail for the PRBS checker.

  • The jesd204_rx_data_valid signal is asserted.
  • The data_error and jesd204_rx_int signals are deasserted.

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