AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel Stratix 10 Devices

ID 683172
Date 12/18/2017
Public

1.6. Test Result Comments

In each test case, the JESD204B receiver IP core successfully initialize from CGS phase, ILA phase, and until user data phase.

No data integrity issue is observed by the PRBS and Ramp checker for all JESD configurations. In one of the JESD configuration modes (LMF=611), the result status is marked with 'Pass with comments' because data integrity tests were not performed. The Intel® FPGA transport layer doesn't support configurations with N'= 12 and F = 1 which is the case with this configuration mode. However, all other test cases were found to be PASS.

In the deterministic latency measurement, consistent total latency is observed across multiple power cycles or resets.

For a few JESD configurations, to avoid lane de-skew error or achieve deterministic latency on FPGA, RBD offset register needs to be programmed. The modes and the corresponding values used are tabled below.

Mode (LMF) csr_rbd_offset (syncn_sysref_ctrl [10:3])
611 K=32 4

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