External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide

Download PDF
ID 683162
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP 3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP 4. External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide Archives 5. Document Revision History for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Generating the Synthesizable EMIF Design Example 2.4. Generating the EMIF Design Example for Simulation 2.5. Simulation Versus Hardware Implementation 2.6. Simulating External Memory Interface IP With ModelSim 2.7. Pin Placement for Intel® Agilex™ 7 F-Series and I-Series EMIF IP 2.8. Compiling and Programming the Intel® Agilex™ 7 F-Series and I-Series EMIF Design Example 2.9. Generating a Design Example with the Calibration Debug Option 2.10. Generating a Design Example with the TG Configuration Option 2.11. Using the Design Example with the EMIF Debug Toolkit
2.2. Generating and Configuring the EMIF IP x
2.2.1. Intel® Agilex™ 7 F-Series and I-Series EMIF Parameter Editor Guidelines
2.10. Generating a Design Example with the TG Configuration Option x
2.10.1. Enabling the Traffic Generator in a Design Example
3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Designs Interface Tab
1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
4. External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide Archives
5. Document Revision History for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide

2.6. Simulating External Memory Interface IP With ModelSim

This procedure shows how to simulate the EMIF design example.

  1. Launch the Mentor Graphics* ModelSim software and select File > Change Directory. Navigate to the sim/ed_sim/mentor directory within the generated design example folder.
  2. Verify that the Transcript window is displayed at the bottom of the screen. If the Transcript window is not visible, display it by clicking View > Transcript.
  3. In the Transcript window, run source msim_setup.tcl.
  4. After source msim_setup.tcl finishes running, run ld_debug in the Transcript window.
  5. After ld_debug finishes running, verify that the Objects window is displayed. If the Objects window is not visible, display it by clicking View > Objects.
  6. In the Objects window, select the signals that you want to simulate by right-clicking and selecting Add Wave.
  7. After you finish selecting the signals for simulation, execute run -all in the Transcript window. The simulation runs until it is completed.
  8. If the simulation is not visible, click View > Wave.
Level Two Title