External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide

ID 683162
Date 4/03/2023
Document Table of Contents

2.2. Generating and Configuring the EMIF IP

The following steps illustrate how to generate and configure the EMIF IP. This walkthrough creates a DDR4 interface, but the steps are similar for other protocols. (These steps follow the IP Catalog (standalone) flow; if you choose to use the Platform Designer (system) flow instead, the steps are similar.)

  1. In the IP Catalog window, select External Memory Interfaces Intel® Agilex™ 7 FPGA IP. (If the IP Catalog window is not visible, select View > IP Catalog.)

  2. In the IP Parameter Editor, provide an entity name for the EMIF IP (the name that you provide here becomes the file name for the IP) and specify a directory. Click Create.

  3. The parameter editor has multiple tabs where you must configure parameters to reflect your EMIF implementation.