External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide

ID 683162
Date 4/03/2023
Document Table of Contents

2.10. Generating a Design Example with the TG Configuration Option

The generated EMIF design example includes a traffic generator block (TG). By default, the design example uses a simple TG block (altera_tg_avl) which can only be reset in order to relaunch a hard-coded traffic pattern. If necessary, you may choose to enable a configurable traffic generator (TG2) instead.

In the configurable traffic generator (TG2) (altera_tg_avl_2), you can configure the traffic pattern in real time through control registers—meaning that you do not have to recompile the design to change or relaunch the traffic pattern. This traffic generator provides fine control over the type of traffic that it sends on the EMIF control interface. Additionally, it provides status registers that contain detailed failure information.