Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

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ID 683152
Date 1/23/2025
Public
Document Table of Contents
Document Table of Contents x
1. Discontinuation of the Intel® HLS Compiler 2. Intel® HLS Compiler Pro Edition Best Practices Guide 3. Best Practices for Coding and Compiling Your Component 4. FPGA Concepts 5. Interface Best Practices 6. Loop Best Practices 7. fMAX Bottleneck Best Practices 8. Memory Architecture Best Practices 9. System of Tasks Best Practices 10. Datatype Best Practices 11. Advanced Troubleshooting A. Intel® HLS Compiler Pro Edition Best Practices Guide Archives B. Document Revision History for Intel® HLS Compiler Pro Edition Best Practices Guide
4. FPGA Concepts x
4.1. FPGA Architecture Overview 4.2. Concepts of FPGA Hardware Design 4.3. Methods of Hardware Design
4.1. FPGA Architecture Overview x
4.1.1. Adaptive Logic Module (ALM) 4.1.2. Digital Signal Processing (DSP) Block 4.1.3. Random-Access Memory (RAM) Blocks
4.1.1. Adaptive Logic Module (ALM) x
4.1.1.1. Lookup Table (LUT) 4.1.1.2. Register
4.2. Concepts of FPGA Hardware Design x
4.2.1. Maximum Frequency (fMAX) 4.2.2. Latency 4.2.3. Pipelining 4.2.4. Throughput 4.2.5. Datapath 4.2.6. Control Path 4.2.7. Occupancy
4.3. Methods of Hardware Design x
4.3.1. How Source Code Becomes a Custom Hardware Datapath 4.3.2. Scheduling 4.3.3. Mapping Parallelism Models to FPGA Hardware 4.3.4. Memory Types
4.3.1. How Source Code Becomes a Custom Hardware Datapath x
4.3.1.1. Mapping Source Code Instructions to Hardware 4.3.1.2. Mapping Arrays and Their Accesses to Hardware
4.3.2. Scheduling x
4.3.2.1. Dynamic Scheduling 4.3.2.2. Clustering the Datapath 4.3.2.3. Handshaking Between Clusters
4.3.3. Mapping Parallelism Models to FPGA Hardware x
4.3.3.1. Data Parallelism 4.3.3.2. Task Parallelism
4.3.3.1. Data Parallelism x
4.3.3.1.1. Executing Independent Operations Simultaneously 4.3.3.1.2. Pipelining
4.3.3.1.2. Pipelining x
4.3.3.1.2.1. Pipelining Loops Within A Component 4.3.3.1.2.2. Pipelining Across Component Invocations
4.3.4. Memory Types x
4.3.4.1. Component Memory 4.3.4.2. External Memory
5. Interface Best Practices x
5.1. Choose the Right Interface for Your Component 5.2. Control LSUs For Your Variable-Latency MM Host Interfaces 5.3. Avoid Pointer Aliasing
5.1. Choose the Right Interface for Your Component x
5.1.1. Pointer Interfaces 5.1.2. Avalon® Memory Mapped Host Interfaces 5.1.3. Avalon® Memory Mapped Agent Memories 5.1.4. Avalon® Memory Mapped Agent Registers 5.1.5. Avalon® Streaming Interfaces 5.1.6. Pass-by-Value Interface
6. Loop Best Practices x
6.1. Reuse Hardware By Calling It In a Loop 6.2. Parallelize Loops 6.3. Construct Well-Formed Loops 6.4. Minimize Loop-Carried Dependencies 6.5. Avoid Complex Loop-Exit Conditions 6.6. Convert Nested Loops into a Single Loop 6.7. Place if-Statements in the Lowest Possible Scope in a Loop Nest 6.8. Declare Variables in the Deepest Scope Possible 6.9. Raise Loop II to Increase fMAX 6.10. Control Loop Interleaving
6.2. Parallelize Loops x
6.2.1. Pipeline Loops 6.2.2. Unroll Loops 6.2.3. Example: Loop Pipelining and Unrolling
7. fMAX Bottleneck Best Practices x
7.1. Balancing Target fMAX and Target II
8. Memory Architecture Best Practices x
8.1. Example: Overriding a Coalesced Memory Architecture 8.2. Example: Overriding a Banked Memory Architecture 8.3. Merge Memories to Reduce Area 8.4. Example: Specifying Bank-Selection Bits for Local Memory Addresses
8.3. Merge Memories to Reduce Area x
8.3.1. Example: Merging Memories Depth-Wise 8.3.2. Example: Merging Memories Width-Wise
9. System of Tasks Best Practices x
9.1. Executing Multiple Loops in Parallel 9.2. Sharing an Expensive Compute Block 9.3. Implementing a Hierarchical Design 9.4. Balancing Capacity in a System of Tasks
9.4. Balancing Capacity in a System of Tasks x
9.4.1. Enable the Intel® HLS Compiler to Infer Data Path Buffer Capacity Requirements 9.4.2. Explicitly Add Buffer Capacity to Your Design When Needed
10. Datatype Best Practices x
10.1. Avoid Implicit Data Type Conversions 10.2. Avoid Negative Bit Shifts When Using the ac_int Datatype
11. Advanced Troubleshooting x
11.1. Component Fails Only In Simulation 11.2. Component Gets Poor Quality of Results
1. Discontinuation of the Intel® HLS Compiler
2. Intel® HLS Compiler Pro Edition Best Practices Guide
3. Best Practices for Coding and Compiling Your Component
4. FPGA Concepts
5. Interface Best Practices
6. Loop Best Practices
7. fMAX Bottleneck Best Practices
8. Memory Architecture Best Practices
9. System of Tasks Best Practices
10. Datatype Best Practices
11. Advanced Troubleshooting
A. Intel® HLS Compiler Pro Edition Best Practices Guide Archives
B. Document Revision History for Intel® HLS Compiler Pro Edition Best Practices Guide

5.1.2. Avalon® Memory Mapped Host Interfaces

By default, pointers in a component are implemented as Avalon® Memory Mapped ( Avalon® MM) host interfaces with default settings. You can mitigate poor performance from the default settings by configuring the Avalon® MM host interfaces.

You can configure the Avalon® MM host interface for the vector addition component example using the ihc::mm_host class as follows: 

component void vector_add(
  ihc::mm_host<int, ihc::aspace<1>, ihc::dwidth<8*8*sizeof(int)>, 
                 ihc::align<8*sizeof(int)> >& a,
  ihc::mm_host<int, ihc::aspace<2>, ihc::dwidth<8*8*sizeof(int)>, 
                 ihc::align<8*sizeof(int)> >& b,
  ihc::mm_host<int, ihc::aspace<3>, ihc::dwidth<8*8*sizeof(int)>, 
                 ihc::align<8*sizeof(int)> >& c,
  int N) {
  #pragma unroll 8
  for (int i = 0; i < N; ++i) {
      c[i] = a[i] + b[i];
  }
}
The memory interfaces for vector a, vector b, and vector c have the following attributes specified:
  • The vectors are each assigned to different address spaces with the ihc::aspace attribute, and each vector receives a separate Avalon® MM host interface.

    With the vectors assigned to different physical interfaces, the vectors can be accessed concurrently without interfering with each other, so memory arbitration is not needed.

  • The width of the interfaces for the vectors is adjusted with the ihc::dwidth attribute.
  • The alignment of the interfaces for the vectors is adjusted with the ihc::align attribute.
The following diagram shows the Function View in the System Viewer that is generated when you compile this example.
Figure 25. System Viewer Function View for vector_add Component with Avalon® MM Host Interface


The diagram shows that vector_add.B2 has two loads and one store. The default Avalon® MM Host settings used by the code example in Pointer Interfaces had 16 loads and 8 stores.

By expanding the width and alignment of the vector interfaces, the original pointer interface loads and stores were coalesced into one wide load each for vector a and vector b, and one wide store for vector c.

Also, the memories are stall-free because the loads and stores in this example access separate memories.

Compiling this component with an Quartus® Prime compilation flow targeting an Arria® 10 device results in the following QoR metrics:
Table 3.  QoR Metrics Comparison for Avalon MM Host Interface1
QoR Metric Pointer Avalon MM Host
ALMs 15593.5 643
DSPs 0 0
RAMs 30 0
fMAX (MHz)2 298.6 472.37
Latency (cycles) 24071 142
Initiation Interval (II) (cycles) ~508 1
1The compilation flow used to calculate the QoR metrics used Quartus® Prime Pro Edition Version 17.1.
2The fMAX measurement was calculated from a single seed.
All QoR metrics improved by changing the component interface to a specialized Avalon® MM Host interface from a pointer interface. The latency is close to the ideal latency value of 128, and the loop initiation interval (II) is 1.
Important: This change to a specialized Avalon® MM Host interface from a pointer interface requires the system to have three separate memories with the expected width. The initial pointer implementation requires only one system memory with a 64-bit wide data bus. If the system cannot provide the required memories, you cannot use this optimization.
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