Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

ID 683152
Date 9/23/2022
Public
Document Table of Contents

7. Memory Architecture Best Practices

The Intel® High Level Synthesis Compiler infers efficient memory architectures (like memory width, number of banks and ports) in a component by adapting the architecture to the memory access patterns of your component. Review the memory architecture best practices to learn how you can get the best memory architecture for your component from the compiler.

In most cases, you can optimize the memory architecture by modifying the access pattern. However, the Intel® HLS Compiler Pro Edition gives you some control over the memory architecture.

Tutorials Demonstrating Memory Architecture Best Practices

The Intel® HLS Compiler Pro Edition comes with a number of tutorials that illustrate important Intel® HLS Compiler concepts and demonstrate good coding practices.

Review the following tutorials to learn about memory architecture best practices that might apply to your design:
Table 7.  Tutorials Provided with Intel® HLS Compiler Pro Edition
Tutorial Description
You can find these tutorials in the following location on your Intel® Quartus® Prime system:
<quartus_installdir>/hls/examples/tutorials/component_memories
attributes_on_mm_agent_arg Demonstrates how to apply memory attributes to Avalon® Memory Mapped (MM) agent arguments.
exceptions Demonstrates how to use memory attributes on constants and struct members.
memory_bank_configuration Demonstrates how to control the number of load/store ports of each memory bank and optimize your component area usage, throughput, or both by using one or more of the following memory attributes:
  • hls_max_replicates
  • hls_singlepump
  • hls_doublepump
  • hls_simple_dual_port_memory
memory_geometry Demonstrates how to control the number of load/store ports of each memory bank and optimize your component area usage, throughput, or both by using one or more of the following memory attributes:
  • hls_bankwidth
  • hls_numbanks
  • hls_bankbits
memory_implementation Demonstrates how to implement variables or arrays in registers, MLABs, or RAMs by using the following memory attributes:
  • hls_register
  • hls_memory
  • hls_memory_impl
memory_merging Demonstrates how to improve resource utilization by implementing two logical memories as a single physical memory by merging them depth-wise or width-wise with the hls_merge memory attribute.
non_trivial_initialization Demonstrates how to use the C++ keyword constexpr to achieve efficient initialization of read-only variables.
non_power_of_two_memory Demonstrates how to use the force_pow2_depth memory attribute to control the padding of memories that are non-power-of-two deep, and how that impacts the FPGA memory resource usage.
static_var_init Demonstrates how to control the initialization behavior of statics in a component using the hls_init_on_reset or hls_init_on_powerup memory attribute.

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