Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

ID 683152
Date 9/23/2022
Document Table of Contents Mapping Arrays and Their Accesses to Hardware

Similar to the mapping of statements to specialized hardware operations, the compiler can map arrays (and structs) to hardware memories based on memory access patterns and variable sizes.

The datapath interacts with this memory through load/store units (LSUs), which are inferred from array accesses in the source code.

The following figure illustrates a simple example of mapping arrays and their accesses to hardware:

A RAM can have a limited number of read ports and write ports, but a datapath can have many LSUs. When the number of LSUs does not match the available number of read and write ports, the compiler uses techniques like replication, double pumping, sharing, and arbitration. For descriptions of these techniques, refer to Component Memory.

FPGAs provide specialized hardware block RAMs that you can configure and combine to match the size of your arrays. Customizing your memory configuration for your design can provide terabytes-per-second of on-chip memory bandwidth because each of these memories can interact with the datapath simultaneously.

Arrays might also be implemented in your component datapath. In this case, the array contents are stored as registers in the datapath when your algorithm is pipelined (as discussed in Pipelining). Storing array contents as registers in the datapath can improve performance in some cases, but it is a design decision whether to implement an array as registers or as memories.

When you access an array that is implemented as registers, LSUs are not used. The compiler might choose to use a select or a barrel shifter instead.

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