6. fMAX Bottleneck Best Practices
Tutorials Demonstrating fMAX Bottleneck Best Practices
The Intel® HLS Compiler Pro Edition comes with a number of tutorials that illustrate important Intel® HLS Compiler concepts and demonstrate good coding practices.
|You can find these tutorials in the following location on your Intel® Quartus® Prime system:
|best_practices/ fpga_reg||Demonstrates how manually adding pipeline registers can increase fMAX|
|best_practices/ overview||Demonstrates how fMAX can depend on the interface used in your component.|
|best_practices/ parallelize_array_operation||Demonstrates how to improve fMAX by correcting a bottleneck that arises when performing operations on an array in a loop.|
|best_practices/ reduce_exit_fifo_width||Demonstrates how to improve fMAX by reducing the width of the FIFO belonging to the exit node of a stall-free cluster|
|best_practices/ relax_reduction_dependency||Demonstrates how fMAX can depend on the loop-carried feedback path.|
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