1. Intel® HLS Compiler Pro Edition Best Practices Guide 2. Best Practices for Coding and Compiling Your Component 3. FPGA Concepts 4. Interface Best Practices 5. Loop Best Practices 6. fMAX Bottleneck Best Practices 7. Memory Architecture Best Practices 8. System of Tasks Best Practices 9. Datatype Best Practices 10. Advanced Troubleshooting A. Intel® HLS Compiler Pro Edition Best Practices Guide Archives B. Document Revision History for Intel® HLS Compiler Pro Edition Best Practices Guide
5.1. Reuse Hardware By Calling It In a Loop 5.2. Parallelize Loops 5.3. Construct Well-Formed Loops 5.4. Minimize Loop-Carried Dependencies 5.5. Avoid Complex Loop-Exit Conditions 5.6. Convert Nested Loops into a Single Loop 5.7. Place if-Statements in the Lowest Possible Scope in a Loop Nest 5.8. Declare Variables in the Deepest Scope Possible 5.9. Raise Loop II to Increase fMAX 5.10. Control Loop Interleaving
6. fMAX Bottleneck Best Practices
The fMAX of your component can be limited for various reasons. Review these best practices to understand some common fMAX bottlenecks and how to mitigate them.
Tutorials Demonstrating fMAX Bottleneck Best Practices
The Intel® HLS Compiler Pro Edition comes with a number of tutorials that illustrate important Intel® HLS Compiler concepts and demonstrate good coding practices.
Review the following tutorials to learn about fMAX bottleneck best practices that might apply to your design:
|You can find these tutorials in the following location on your Intel® Quartus® Prime system:
|Demonstrates how manually adding pipeline registers can increase fMAX
|Demonstrates how fMAX can depend on the interface used in your component.
|Demonstrates how to improve fMAX by correcting a bottleneck that arises when performing operations on an array in a loop.
|Demonstrates how to improve fMAX by reducing the width of the FIFO belonging to the exit node of a stall-free cluster
|Demonstrates how fMAX can depend on the loop-carried feedback path.