Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

ID 683152
Date 3/28/2022
Public

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3.3.3.1. Data Parallelism

Traditional instruction-set-architecture-based (ISA-based) accelerators, such as GPUs, derive data parallelism from vectorized instructions and by executing the same operation on multiple processing units.

In comparison, FPGAs derive their performance by taking advantage of their spatial architecture. FPGA compilers do not require you to vectorize your code. The compiler vectorizes your code automatically whenever it can.

The generated hardware implements data parallelism in the following ways:

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