Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

ID 683152
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

When a loop nest has an inner loop II that is greater than 1, the Intel® HLS Compiler can attempt to interleave iterations of the outer loop into iterations of the inner loop to better utilize the hardware resources and achieve higher throughput.

Figure 18. Interleaving

For additional information about controlling interleaving in your component, refer to Loop Interleaving Control (max_interleaving Pragma) in the Intel® High Level Synthesis Compiler Reference Manual .

Did you find the information on this page useful?

Characters remaining:

Feedback Message