Early Power Estimator for Intel® Cyclone® 10 GX FPGAs User Guide

ID 683150
Date 12/03/2021
Public
Document Table of Contents

4.9. Cyclone® 10 GX EPE - I/O-IP Worksheet

Each row in the I/O-IP worksheet of the Early Power Estimator (EPE) for Cyclone® 10 GX represents a design module. You use the I/O-IP worksheet to instantiate external memory interface IPs supported in Cyclone® 10 GX. The I/O-IP worksheet populates other EPE worksheets with resources used by a selected IP.

Analog I/O power and digital power of hard memory controller IPs entered on this tab are reported in the Analog Power and Digital Power fields of the I/O worksheet. If the IP uses other resource types (for example Logic or PLL), the power is reported on the corresponding worksheet.

Figure 20. I/O-IP Worksheet of the Early Power Estimator


I/O-IP Worksheet Information

Column Heading Description
Module Specify a name for the IP in this column. The module name depends on the selected IP type. It helps to cross-reference each IP module and its corresponding auto-populated entries on other worksheets.
IP Specifies the name of the IP in the design.
Voltage Specifies the I/O voltage of the signaling between periphery device and interface.
Data Width (Bits) Specifies the interface data width of the specific IP (in bits).
Data Group Width Specifies the number of DQ pins per data group.
Memory Device(s) Specifies the number of memory devices connected to the interface.
Address Width Specifies the address width. This value is used to derive the total number of address pins required.
DDR Rate Specifies the clock rate of user logic. Determines the clock frequency of user logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that the user logic in the FPGA runs at 200MHz.
PHY Rate Specifies the clock rate of PHY logic. Determines the clock frequency of PHY logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that the PHY logic in the FPGA runs at 200MHz.
Memory Clock Freq (MHz) Specifies the frequency of memory clock (in MHz).
PLL Reference Clock Freq (MHz) Specifies the PLL Reference Clock Frequency (in MHz).
User Comments Enter any comments. This is an optional entry.

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