Reed-Solomon II IP Core User Guide

ID 683144
Date 5/02/2016

2.4. Simulating Altera IP Cores

The Quartus® Prime software supports RTL and gate-level simulation of Altera IP cores in supported EDA simulators. The Quartus® Prime software generates simulation files for each IP core during IP generation, including the functional simulation model, any testbench (or example design), and vendor-specific simulator setup scripts for each IP core. You can use the functional simulation model and the testbench or example design generated with your IP core for simulation. The IP generation output also includes scripts to compile and run any testbench. The generated scripts list all models or libraries required to simulate your IP core.

The Quartus® Prime software provides integration with your simulator and supports multiple simulation flows, including your own scripted and custom simulation flows. Whichever flow you chose, IP core simulation involves the following steps:

  1. Generate simulation model, testbench (or example design), and simulator setup script files.
  2. Set up your simulator environment and any simulation script(s).
  3. Compile simulation model libraries.
  4. Run your simulator.

The Quartus® Prime software integrates with your preferred simulation environment. This section describes how to setup and run typical scripted and NativeLink simulation flows. The Quartus® Prime Pro Edition software does not support NativeLink simulation.

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