Reed-Solomon II IP Core User Guide

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ID 683144
Date 11/17/2015
Public
Document Table of Contents
Document Table of Contents x
1. About the Reed-Solomon II IP Core 2. Reed-Solomon II IP Core Getting Started 3. Reed-Solomon II IP Core Functional Description 4. Document Revision History
1. About the Reed-Solomon II IP Core x
1.1. Altera DSP IP Core Features 1.2. Reed-Solomon II IP Core Features 1.3. DSP IP Core Device Family Support 1.4. DSP IP Core Verification 1.5. Reed-Solomon II IP Core Release Information 1.6. Reed-Solomon II IP Core Performance and Resource Utilization
2. Reed-Solomon II IP Core Getting Started x
2.1. Licensing IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores 2.4. Simulating Altera IP Cores in other EDA Tools 2.5. DSP Builder Design Flow
2.1. Licensing IP Cores x
2.1.1. OpenCore Plus IP Evaluation 2.1.2. Reed-Solomon II IP Core OpenCore Plus Timeout Behavior
2.3. Generating IP Cores x
2.3.1. Files Generated for Altera IP Cores and Qsys Systems
3. Reed-Solomon II IP Core Functional Description x
3.1. Architecture 3.2. Reed-Solomon II IP Core Parameters 3.3. Reed-Solomon II IP Core Interfaces and Signals
3.1. Architecture x
3.1.1. Reed-Solomon II Encoder 3.1.2. Reed-Solomon II Decoder 3.1.3. Multiple Input Channels
3.3. Reed-Solomon II IP Core Interfaces and Signals x
3.3.1. Avalon-ST Interfaces in DSP IP Cores 3.3.2. Reed-Solomon II IP Core Signals
1. About the Reed-Solomon II IP Core
2. Reed-Solomon II IP Core Getting Started
3. Reed-Solomon II IP Core Functional Description
4. Document Revision History

2.4. Simulating Altera IP Cores

The Quartus® Prime software supports RTL and gate-level simulation of Altera IP cores in supported EDA simulators. The Quartus® Prime software generates simulation files for each IP core during IP generation, including the functional simulation model, any testbench (or example design), and vendor-specific simulator setup scripts for each IP core. You can use the functional simulation model and the testbench or example design generated with your IP core for simulation. The IP generation output also includes scripts to compile and run any testbench. The generated scripts list all models or libraries required to simulate your IP core.

The Quartus® Prime software provides integration with your simulator and supports multiple simulation flows, including your own scripted and custom simulation flows. Whichever flow you chose, IP core simulation involves the following steps:

  1. Generate simulation model, testbench (or example design), and simulator setup script files.
  2. Set up your simulator environment and any simulation script(s).
  3. Compile simulation model libraries.
  4. Run your simulator.

The Quartus® Prime software integrates with your preferred simulation environment. This section describes how to setup and run typical scripted and NativeLink simulation flows. The Quartus® Prime Pro Edition software does not support NativeLink simulation.

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