Reed-Solomon II IP Core User Guide

ID 683144
Date 5/02/2016
Public

2.3.1. Files Generated for Altera IP Cores and Qsys Systems

The Quartus® Prime software generates the following output file structure for IP cores and Qsys systems. The generated .qsys file must be added to your project to represent IP and Qsys systems. For devices released prior to Arria 10 devices, the generated .qip and .sip files must be added to your Quartus® Prime Standard Edition project to represent IP and Qsys systems
Figure 3. Files generated for IP cores and Qsys Systems


Table 4.  IP Core and Qsys Simulation Generated Files

File Name

Description

<my_ip>.qsys

The Qsys system or top-level IP variation file.

<system>.sopcinfo

Describes the connections and IP component parameterizations in your Qsys system. You can parse the contents of this file to get requirements when you develop software drivers for IP components.

Downstream tools such as the Nios II tool chain use this file. The .sopcinfo file and the system.h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component.

<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.
<my_ip>.html

A report that contains connection information, a memory map showing the slave address with respect to each master that the slave connects to, and parameter assignments.

<my_ip>_generation.rpt IP or Qsys generation log file. A summary of the messages during IP generation.
<my_ip>.debuginfo Contains post-generation information. Passes System Console and Bus Analyzer Toolkit information about the Qsys interconnect. The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect.
<my_ip>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the Quartus® Prime software.

<my_ip>.csv Contains information about the upgrade status of the IP component.

<my_ip>.bsf

A Block Symbol File (.bsf) representation of the IP variation for use in Quartus® Prime Block Diagram Files (.bdf).

<my_ip>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<my_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner.
<my_ip>_bb.v You can use the Verilog blackbox (_bb.v) file as an empty module declaration for use as a blackbox.
<my_ip>.sip Contains information required for NativeLink simulation of IP components. You must add the .sip file to your Quartus project to enable NativeLink for Arria II, Arria V, Cyclone IV, Cyclone V, MAX 10, MAX II, MAX V, Stratix IV, and Stratix V devices. The Quartus® Prime Pro Edition does not support NativeLink simulation.
<my_ip>_inst.v or _inst.vhd HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation.
<my_ip>.regmap If the IP contains register information, the Quartus® Prime software generates the .regmap fil. The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console.
<my_ip>.svd

Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system.

During synthesis, the Quartus® Prime software stores the .svd files for slave interface visible to the System Console masters in the .sof file in the debug session. System Console reads this section, which Qsys can query for register map information. For system slaves, Qsys can access the registers by name.

<my_ip>.v <my_ip>.vhd HDL files that instantiate each submodule or child IP core for synthesis or simulation.
mentor/

Contains a ModelSim® script msim_setup.tcl to set up and run a simulation.

aldec/

Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation.

/synopsys/vcs

/synopsys/vcsmx

Contains a shell script vcs_setup.sh to set up and run a VCS® simulation.

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS MX® simulation.

/cadence

Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation.

/submodules Contains HDL files for the IP core submodule.
<IP submodule>/ For each generated IP submodule directory, Qsys generates /synth and /sim sub-directories.

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