F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 8/19/2024
Public
Document Table of Contents

2.5. Performance and Resource Utilization

The following table shows the recommended FPGA fabric speed grades for all the configurations that the Avalon® -ST IP core supports.

Table 5.   Agilex™ 7 Recommended FPGA Fabric Speed Grades for All Avalon-ST Widths and FrequenciesThe recommended FPGA fabric speed grades are for production parts.

Lane Rate

Link Configuration

Application Interface Data Width

Application Clock Frequency (MHz)

Recommended FPGA Fabric Speed Grades

Gen4 1 x16 512-bit 500 MHz/ 450 MHz / 400 MHz / 350 MHz / 250 MHz / 225 MHz / 200 MHz / 175 MHz -1,-2
450 MHz / 400 MHz / 350 MHz / 225 MHz / 200 MHz / 175 MHz -3
1 x8 256-bit 500 MHz/ 450 MHz / 400 MHz / 350 MHz -1,-2
450 MHz / 400 MHz / 350 MHz -3
2 x8

512-bit 1

250 MHz / 225 MHz / 200 MHz / 175 MHz -1,-2
225 MHz / 200 MHz / 175 MHz -3
256-bit 500 MHz/ 450 MHz / 400 MHz / 350 MHz / 250 MHz / 225 MHz / 200 MHz / 175 MHz -1,-2
450 MHz / 400 MHz / 350 MHz / 225 MHz / 200 MHz / 175 MHz -3
1x4 128-bit 500 MHz/ 450 MHz / 400 MHz /350 MHz -1,-2
450 MHz / 400 MHz / 350 MHz -3
2 x4 128-bit 500 MHz/ 450 MHz / 400 MHz / 350 MHz -1,-2
450 MHz / 400 MHz / 350 MHz -3
4 x4 128-bit 500 MHz / 450 MHz / 400 MHz / 350 MHz -1,-2
450 MHz / 400 MHz / 350 MHz -3
Gen3 1 x16 512-bit 250 MHz -1,-2,-3

256-bit 2

250 MHz -1,-2,-3
1 x8 256-bit 250 MHz -1,-2,-3
2 x8 256-bit 250 MHz -1,-2,-3
1 x4 128-bit 250 MHz -1,-2,-3
2 x4 128-bit 250 MHz -1,-2,-3
4 x4 128-bit 250 MHz -1,-2,-3
Note: Select the highest clock frequency to achieve maximum PCIe Gen4 bandwidth.

The following table shows the typical resource utilization information for selected configurations.

The resource usage is based on the Avalon® -ST IP core top-level entity (intel_pcie_ftile_ast) that includes IP core soft logic implemented in the FPGA fabric.

Table 6.  Resource Utilization Information of the IP
IP Configuration Device Family ALMs M20Ks Logic Registers
Gen4 x16, EP Agilex™ 7 11,709 10 19,506
Gen4 x16, RP Agilex™ 7 11,749 10 19,387
Gen4 x8x8, EP Agilex™ 7 12,074 10 19,856
Gen4 x8, EP Agilex™ 7 9,951 10 15,479
Gen4 x8, RP Agilex™ 7 10,013 10 15,514
Gen4 x4, EP Agilex™ 7 9,475 10 14,417
Gen4 x4, RP Agilex™ 7 9,593 10 14,570
Gen4 x4x4, RP Agilex™ 7 11,243 10 17,782
Gen4 x4x4x4x4, RP Agilex™ 7 14,640 10 24,672
Note: The default IP parameter is used for each of the IP configurations above, resource utilization may increase as additional IP features enabled. The resource utilization of the IP above has taken the tile logic into account.

1 In this configuration, interface width increased to support lower application clock frequency.
2 In this configuration, interface efficiency is traded off for lower interface width.