F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 8/19/2024
Public
Document Table of Contents

5.6. Hard IP Status Interface

This interface includes the signals that are useful for debugging, such as the link status signal, LTSSM state outputs, etc. These signals are available when the optional Power Management interface is enabled.

Table 67.  Hard IP Status Interface SignalsEP=Endpoint; RP=Root Port; BP=TLP Bypass; DN=Downstream Port
Signal Name Direction Port Type Clock Domain Description
p#_link_up_o Output EP/RP/BP coreclkout_hip When asserted, this signal indicates the link is up.
p#_dl_up_o Output EP/RP/BP coreclkout_hip When asserted, this signal indicates the Data Link (DL) Layer is active.
p#_ltssm_state_o Output EP/RP/BP coreclkout_hip
Indicates the LTSSM state:
  • 6'h00: S_DETECT_QUIET
  • 6'h01: S_DETECT_ACT
  • 6'h02: S_POLL_ACTIVE
  • 6'h03: S_POLL_COMPLIANCE
  • 6'h04: S_POLL_CONFIG
  • 6'h05: S_PRE_DETECT_QUIET
  • 6'h06: S_DETECT_WAIT
  • 6'h07: S_CFG_LINKWD_START
  • 6'h08: S_CFG_LINKWD_ACCEPT
  • 6'h09: S_CFG_LANENUM_WAIT
  • 6'h0A: S_CFG_LANENUM_ACCEPT
  • 6'h0B: S_CFG_COMPLETE
  • 6'h0C: S_CFG_IDLE
  • 6'h0D: S_RCVRY_LOCK
  • 6'h0E: S_RCVRY_SPEED
  • 6'h0F: S_RCVRY_RCVRCFG
  • 6'h10: S_RCVRY_IDLE
  • 6'h11: S_L0
  • 6'h12: S_L0S
  • 6'h13: S_L123_SEND_EIDLE
  • 6'h14: S_L1_IDLE
  • 6'h15: S_L2_IDLE
  • 6'h16: S_L2_WAKE
  • 6'h17: S_DISABLED_ENTRY
  • 6'h18: S_DISABLED_IDLE
  • 6'h19: S_DISABLED
  • 6'h1A: S_LPBK_ENTRY
  • 6'h1B: S_LPBK_ACTIVE
  • 6'h1C: S_LPBK_EXIT
  • 6'h1D: S_LPBK_EXIT_TIMEOUT
  • 6'h1E: S_HOT_RESET_ENTRY
  • 6'h1F: S_HOT_RESET
  • 6'h20: S_RCVRY_EQ0
  • 6'h21: S_RCVRY_EQ1
  • 6'h22: S_RCVRY_EQ2
  • 6'h23: S_RCVRY_EQ3
p#_surprise_down_err_o Output BP DN Async

Indicates that a surprise down event is occurring in the controller.