AN 769: Altera® FPGA Remote Temperature Sensing Diode Implementation Guide

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ID 683139
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Implementation Overview 3. Implementation Consideration 4. Evaluation Results 5. Conclusion 6. Document Revision History for AN 769: Altera® FPGA Remote Temperature Sensing Diode Implementation Guide
3. Implementation Consideration x
3.1. Ideality Factor (η-Factor) Mismatch 3.2. Series Resistance Error 3.3. Temperature Diode Beta Variation 3.4. Differential Input Capacitor 3.5. Offset Compensation
4. Evaluation Results x
4.1. Evaluation with Maxim Integrated* 's MAX31730 Temperature Sensing Chip Evaluation Board 4.2. Evaluation with Texas Instruments* 's TMP468 Temperature Sensing Chip Evaluation Board
1. Introduction
2. Implementation Overview
3. Implementation Consideration
4. Evaluation Results
5. Conclusion
6. Document Revision History for AN 769: Altera® FPGA Remote Temperature Sensing Diode Implementation Guide

4.2. Evaluation with Texas Instruments* 's TMP468 Temperature Sensing Chip Evaluation Board

This evaluation was conducted with setup steps as described in the Offset Compensation section.

The data was collected before and after applying the offset compensation. Different offset temperature was applied to different Altera® FPGA blocks because a single offset value cannot be applied on all blocks. The following figures show the results.

Figure 12. Data for Stratix® 10 Core Fabric


Figure 13. Data for Altera® FPGA H-Tile and L-Tile


Figure 14. Data for Altera® FPGA E-Tile


Figure 15. Data for Altera® FPGA P-Tile


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