GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683136
Date 9/13/2023
Public
Document Table of Contents
Document Table of Contents x
GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information for GPIO Intel® FPGA IP GPIO Intel® FPGA IP Features GPIO Intel® FPGA IP Data Paths GPIO Intel® FPGA IP Interface Signals Verifying Resource Utilization and Design Performance GPIO Intel® FPGA IP Parameter Settings Register Packing GPIO Intel® FPGA IP Timing GPIO Intel® FPGA IP Design Examples IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices Intel® Arria® 10 and Intel® Cyclone® 10 GX GPIO Intel® FPGA IP User Guide Archives Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
GPIO Intel® FPGA IP Data Paths x
Input Path Output and Output Enable Paths
GPIO Intel® FPGA IP Interface Signals x
Shared Signals Data Bit-Order for Data Interface Input and Output Bus High and Low Bits Data Interface Signals and Corresponding Clocks
GPIO Intel® FPGA IP Timing x
Timing Components Delay Elements Timing Analysis Timing Closure Guidelines
Timing Analysis x
Single Data Rate Input Register Full-Rate or Half-Rate DDIO Input Register Single Data Rate Output Register Full-Rate or Half-Rate DDIO Output Register
GPIO Intel® FPGA IP Design Examples x
GPIO Intel® FPGA IP Synthesizable Intel® Quartus® Prime Design Example GPIO Intel® FPGA IP Simulation Design Example
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores Guideline: Swap datain_h and datain_l Ports in Migrated IP
GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices

The IP migration flow allows you to migrate the ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP cores of Arria® V, Cyclone® V, and Stratix® V devices to the GPIO IP core of Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

This IP migration flow configures the GPIO IP core to match the settings of the ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP cores, allowing you to regenerate the IP core.

Note: Some IP cores support the IP migration flow in specific modes only. If your IP core is in a mode that is not supported, you may need to run the IP Parameter Editor for the GPIO IP core and configure the IP core manually.

Section Content
Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores
Guideline: Swap datain_h and datain_l Ports in Migrated IP

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