Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

22.3.2.5. EPCQ_FLAG_STATUS

Table 245.  EPCQ_FLAG_STATUS
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved flag_status

Upon reading the register, flag_status field gathers information from flash status register as shown in Table 244. To clear the flag status register, write value of 0 to the EPCQ_FLAG_STATUS register. Any value other than 0 is illegal.

Note: Intel recommends that you check the error bits in the EPCQ_FLAG_STATUS register after erase and write commands. You are required to clear the register if error bits are asserted.
Table 246.  EPCQ_FLAG_STATUS Fields
Bit Name Description Access Default Value
31:8 Reserved Reserved 0x0
7 Write or Erase Controller
Indicate whether an operation is in progress:
  • 1=Ready
  • 0=Busy

Refer to the flash datasheet for the list of operations.

R 0x0
6 Erase suspend
Indicate whether an Erase operation is suspended.
  • 1=Erase suspended
  • 0=Clear
R 0x0
5 Erase
Indicate whether an Erase operation is successful.
  • 1=Failure or protection error
  • 0=Clear
RW 0x0
4 Program
Indicate whether a Program operation is successful.
  • 1=Failure or protection error
  • 0=Clear
RW 0x0
3 Reserved Reserved 0x0
2 Program suspend
Indicate whether a Program operation is suspended.
  • 1=Program suspended
  • 0=Clear
R 0x0
1 Protection
Indicate whether an Erase or Program operation is modifying a protected array sector.
  • 1=Protection error
  • 0=Clear
RW 0x0
0 Addressing
Addressing mode used.
  • 1=4-byte addressing
  • 0=3-byte addressing
R 0x0