Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

49.6.1.3. Interface Signals

Figure 163. Interface Signals
Table 470.  peri_clock

Interface Name: peri_clock

Description: Peripheral clock interface. This interface exists only when the selected device is Arria® V or Cyclone® V.

Signal Width Direction Description
clk 1 Input Peripheral clock source used for Avalon® -MM agent interface.
Table 471.  peri_reset

Interface Name: peri_reset

Description: Peripheral reset interface. This interface exists only when the selected device is Arria® V or Cyclone® V.

Signal Width Direction Description
rst_n 1 Input

Active low peripheral asynchronous reset source used to reset the Avalon® -MM agent interface.

This signal is asynchronously asserted and synchronously de-asserted. The synchronous de-assertion must be provided external to this core.

Table 472.  avalon_slave

Interface Name: avalon_slave

Description: This interface exists only when the selected device is Arria® V or Cyclone® V.

Signal Width Direction Description
addr 1 Input Avalon® -MM address bus. 47
read 1 Input Avalon® -MM read control
write 1 Input Avalon® -MM write control
writedata 32 Input Avalon® -MM write data bus
readdata 32 Output Avalon® -MM read data bus
Table 473.  emac

Interface Name: emac

Description: Conduit interface connected to HPS EMAC interface

Signal Width Direction Description
phy_txd_o 8 Input GMII/MII transmit data from HPS
phy_txen_o 1 Input GMII/MII transmit enable from HPS
phy_txer_o 1 Input GMII/MII transmit error from HPS
phy_rxdv_i 1 Output GMII/MII receive data valid to HPS
phy_rxer_i 1 Output GMII/MII receive data error to HPS
phy_rxd_i 8 Output GMII/MII receive data to HPS
phy_col_i 1 Output GMII/MII collision detect to HPS
phy_crs_i 1 Output GMII/MII carrier sense to HPS
phy_mac_speed_o 2 Input MAC speed indication from HPS
mdo_o 1 Input MDIO data output from HPS
mdo_o_e 1 Input MDIO data output enable from HPS
mdi_i 1 Output MDIO data input to HPS
ptp_pps_o 1 Input PTP pulse per second from HPS
ptp_aux_ts_trig_i 1 Output PTP auxiliary timestamp trigger to HPS
Table 474.  emac_gtx_clk

Interface Name: emac_gtx_clk

Description: GMII/MII transmit clock from HPS

Signal Width Direction Description
phy_txclk_o 1 Input GMII/MII transmit clock from HPS
Table 475.  emac_tx_reset

Interface Name: emac_tx_reset

Description: GMII/MII transmit reset source synchronous to phy_txclk_o from HPS

Signal Width Direction Description
rst_tx_n_o 1 Input GMII/MII transmit reset source from HPS. Active low reset.
Table 476.  emac_rx_reset

Interface Name: emac_rx_reset

Description: GMII/MII receive reset source synchronous to clk_rx_i from HPS

Signal Width Direction Description
rst_rx_n_o 1 Input GMII/MII receive reset source from HPS. Active low reset.
Table 477.  emac_rx_clk_in

Interface Name: emac_rx_clk_in

Description: GMII/MII receive clock to HPS

Signal Width Direction Description
clk_rx_i 1 Output GMII/MII receive clock to HPS
Table 478.  emac_tx_clk_in

Interface Name: emac_tx_clk_in

Description: GMII/MII transmit clock to HPS

Signal Width Direction Description
clk_tx_i 1 Output GMII/MII transmit clock to HPS
Table 479.  hps_gmii

Interface Name: hps_gmii

Description: GMII/MII interface facing FPGA fabric

Signal Width Direction Description
mac_tx_clk_o 1 Output GMII/MII transmit clock from HPS
mac_tx_clk_i 1 Input GMII/MII transmit clock to HPS
mac_rx_clk 1 Input GMII/MII receive clock to HPS
mac_rst_tx_n 1 Output GMII/MII transmit reset source from HPS
mac_rst_rx_n 1 Output GMII/MII receive reset source from HPS
mac_txd 8 Output GMII/MII transmit data from HPS
mac_txen 1 Output GMII/MII transmit enable from HPS
mac_txer 1 Output GMII/MII transmit error from HPS
mac_rxdv 1 Input GMII/MII receive data valid to HPS
mac_rxer 1 Input GMII/MII receive data error to HPS
mac_rxd 8 Input GMII/MII receive data to HPS
mac_col 1 Input GMII/MII collision detect to HPS
mac_crs 1 Input GMII/MII carrier sense to HPS
mac_speed 2 Output MAC speed indication from HPS
Table 480.  ptp

Interface Name: ptp

Description: PTP interface facing FPGA fabric

Signal Width Direction Description
ptp_pps_out 1 Output PTP pulse per second to FPGA soft logic
ptp_aux_ts_trig_in 1 Input PTP auxiliary timestamp trigger from FPGA soft logic
ptp_tstmp_data_out 1 Output PTP timestamp data from HPS to FPGA soft logic
ptp_tstmp_en_out 1 Output PTP timestamp enable from HPS to FPGA soft logic
Table 481.  mdio

Interface Name: mdio

Description: MDIO interface facing PHY device

Signal Width Direction Description
mdo_out 1 Output MDIO data output to FPGA bidirectional I/O buffer
mdo_out_en 1 Output MDIO data output enable to FPGA bidirectional I/O buffer
mdi_in 1 Input MDIO data input from FPGA bidirectional I/O buffer
47 The address bus is in the unit of Word addressing.