Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

55.2.4. Handshaking Signal (CTS/RTS Flow Control)

Lightweight UART Core support full-duplex data transmission. If parameter Include CTS/RTS is enabled, the Lightweight UART Core will include handshaking signal which are rts_n (request to send) and cts_n (clear to send). Output of rts_n signal is used to indicate if the core is ready to accept new data and read cts_n to check if the core is allowed to send data to the other device.

When Lightweight UART core acts as a transmitter, you should assert rts_n by writing to RTS bit of control register at address offset 0x3 to request for data transmission. You should monitor the cts_n signal by reading CTS bit of status register at address offset 0x2 to check if the core is allowed to send data to the other device. Data transmission will take place when the Lightweight UART Core receives asserted cts_n signal. Txdata that have been written into TXFIFO will be shifted out via TXD stream.

As described in the following figure, if data transmission has been stopped by cts_n signal deasserted by the other device, the transmit shift register will stop loading the next txdata from the TXFIFO until cts_n is asserted again. Note that the core will still continue to shift out the remaining bits of the txdata that has been loaded in transmit shift register via TXD stream until the transmit shift register is empty. You can de-assert rts_n when transmit data empty bit of status register is HIGH to indicate the completion of data transfer.

Figure 186. Flow Control in Lightweight UART Transmitter

When the Lightweight UART core acts as a receiver, before asserting rts_n, you should read the RXFIFO almost full bit of status register at address offset 0x2 to check if the Lightweight UART core is ready to accept new data from RXD stream.

As described in the following figure, during data transmission, when RXFIFO hits almost full, the Lightweight UART Core will de-assert rts_n automatically to halt data transmission to indicate that the core is not ready to accept new data. You should read out rxdata from RXFIFO in order to resume data transmission process. When the core detect RXFIFO is not almost full, the IP will re-assert back rts_n automatically to accept new data. The remaining RXFIFO depth to assert almost full status can be configurable in GUI.

Figure 187. Flow Control in Lightweight UART Receiver
Note: When the Include CTS/RTS parameter is not enabled, the Lightweight UART transmitter will shift out all the txdata in TXFIFO and transmit shift register continuously until it is empty. Moreover, the Lightweight UART receiver may experience data loss due RXFIFO overflow because it is unable to halt data transmission when RXFIFO is full.