Embedded Peripherals IP User Guide

ID 683130
Date 12/13/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

40.2. Resource Utilization and Performance

Resource utilization and performance for the test pattern generator and checker cores depend on the data width, number of channels, and whether the streaming data uses the optional packet protocol.
Table 405.  Test Pattern Generator Estimated Resource Utilization and Performance
No. of Channels Datawidth (No. of 8-bit Symbols Per Beat) Packet Support Stratix® II and Stratix®  II GX Cyclone® II Stratix®
fMAX

(MHz)

ALM

Count

Memory (bits) fMAX

(MHz)

Logic Cells Memory (bits) fMAX

(MHz)

Logic Cells Memory (bits)
1 4 Yes 284 233 560 206 642 560 202 642 560
1 4 No 293 222 496 207 572 496 245 561 496
32 4 Yes 276 270 912 210 683 912 197 707 912
32 4 No 323 227 848 234 585 848 220 630 848
1 16 Yes 298 361 560 228 867 560 245 896 560
1 16 No 340 330 496 230 810 496 228 845 496
32 16 Yes 295 410 912 209 954 912 224 956 912
32 16 No 269 409 848 219 842 848 204 912 848
Table 406.  Test Pattern Checker Estimated Resource Utilization and Performance
No. of Channels Datawidth (No. of 8-bit Symbols Per Beat) Packet Support Stratix®  II and Stratix®  II GX Cyclone®  II Stratix®
fMAX

(MHz)

ALM

Count

Memory (bits) fMAX

(MHz)

Logic Cells Memory (bits) fMAX

(MHz)

Logic Cells Memory (bits)
1 4 Yes 270 271 96 179 940 0 174 744 96
1 4 No 371 187 32 227 628 0 229 663 32
32 4 Yes 185 396 3616 111 875 3854 105 795 3616
32 4 No 221 363 3520 133 686 3520 133 660 3520
1 16 Yes 253 462 96 185 1433 0 166 1323 96
1 16 No 277 306 32 218 1044 0 192 1004 32
32 16 Yes 182 582 3616 111 1367 3584 110 1298 3616
32 16 No 218 473 3520 129 1143 3520 126 1074 3520