Embedded Peripherals IP User Guide

ID 683130
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

52.3. Interface Signals

Figure 158. Interface Signals
Signal Width Direction Description
Peripheral Clock Interface (peri_clock)
clk 1 Input Peripheral clock source
Peripheral Reset Interface (peri_reset)
rst_n 1 Input

Active-low peripheral asynchronous reset source.

This signal is asynchronously asserted and synchronously de-asserted. The synchronous de-assertion must be provided external to this core.

PLL Clock Interface (pll_derived_clock_in)
pll_125m_clk 1 Input 125MHz derived clock for adapter operation.
pll_25m_clk 1 Input 25MHz derived clock for adapter operation.
pll_2_5m_clk 1 Input 2.5MHz derived clock for adapter operation.
pll_locked 1 Input PLL locked for adapter operation.
Avalon MM Agent Interface for CSR Access (avalon_slave)
addr 1 Input Avalon® Memory-Mapped Interface address bus. The address bus is in the unit of Word addressing.
read 1 Input Avalon® Memory-Mapped Interface read control.
write 1 Input Avalon® Memory-Mapped Interface write control.
writedata 32 Input Avalon® Memory-Mapped Interface write data bus.
readdata 32 Output Avalon® Memory-Mapped Interface read data bus.
HPS EMAC GMII/MII Interface (hps_gmii)
mac_tx_clk_o 1 Input GMII/MII transmit clock from HPS.
mac_tx_clk_i 1 Output GMII/MII transmit clock to HPS.
mac_rx_clk 1 Output GMII/MII receive clock to HPS.
mac_rst_tx_n 1 Input GMII/MII transmit reset source from HPS. Active low reset.
mac_rst_rx_n 1 Input GMII/MII receive reset source from HPS. Active low reset.
mac_txd 8 Input GMII/MII transmit data from HPS.
mac_txen 1 Input GMII/MII transmit enable from HPS.
mac_txer 1 Input GMII/MII transmit error from HPS.
mac_rxdv 1 Output GMII/MII receive data valid to HPS.
mac_rxer 1 Output GMII/MII receive data error to HPS.
mac_rxd 8 Output GMII/MII receive data to HPS.
mac_col 1 Output GMII/MII collision detect to HPS.
mac_crs 1 Output GMII/MII carrier sense to HPS.
mac_speed 2 Input MAC speed indication from HPS.
Multirate PHY GMII Clock Interface
phy_rx_clkout 1 Input Multirate PHY RX Clock Out.
phy_rx_clkena 1 Input Multirate PHY RX Clock Enable.
phy_tx_clkout 1 Input Multirate PHY TX Clock Out.
phy_tx_clkena 1 Input Multirate PHY TX Clock Enable.
Multirate PHY GMII Data Interface (16-bit)
gmii16b_rx_d 16 Input Multirate PHY GMII receive data.
gmii16b_rx_dv 2 Input Multirate PHY GMII receive data valid.
gmii16b_rx_err 2 Input Multirate PHY GMII receive data error.
gmii16b_tx_d 16 Output Multirate PHY GMII transmit data.
gmii16b_tx_en 2 Output Multirate PHY GMII transmit data enable.
gmii16b_tx_err 2 Output Multirate PHY GMII transmit data error.
Multirate PHY Speed Interface
phy_speed 3 Input Multirate PHY Operating Speed.