Embedded Peripherals IP User Guide

ID 683130
Date 12/13/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

43.1.1. Resource Usage and Performance

Resource utilization for the cores depends upon the number of input and output interfaces, the width of the datapath and whether the streaming data uses the optional packet protocol. For the multiplexer, the parameterization of the scheduler also effects resource utilization.
Table 424.  Multiplexer Estimated Resource Usage and Performance
No. of Inputs Data Width Scheduling Size (Cycles) Stratix® II and Stratix®  II GX

(Approximate LEs)

Cyclone® II Stratix®
fMAX

(MHz)

ALM

Count

fMAX

(MHz)

Logic Cells fMAX

(MHz)

Logic Cells
2 Y 1 500 31 420 63 422 80
2 Y 2 500 36 417 60 422 58
2 Y 32 451 43 364 68 360 49
8 Y 2 401 150 257 233 228 298
8 Y 32 356 151 219 207 211 123
16 Y 2 262 333 174 533 170 284
16 Y 32 310 337 161 471 157 277
2 N 1 500 23 400 48 422 52
2 N 9 500 30 420 52 422 56
11 N 9 292 275 197 397 182 287
16 N 9 262 295 182 441 179 224

The core operating frequency varies with the device, the number of interfaces and the size of the datapath.

Table 425.  Demultiplexer Estimated Resource Usage
No. of Inputs Data Width (Symbols per Beat) Stratix®  II

(Approximate LEs)

Cyclone®  II Stratix®  II GX

(Approximate LEs)

fMAX

(MHz)

ALM Count fMAX

(MHz)

Logic Cells fMAX

(MHz)

Logic Cells
2 1 500 53 400 61 399 44
15 1 349 171 235 296 227 273
16 1 363 171 233 294 231 290
2 2 500 85 392 97 381 71
15 2 352 247 213 450 210 417
16 2 328 280 218 451 222 443