Embedded Peripherals IP User Guide

ID 683130
Date 12/13/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

2.5.2. Register Map

You can configure the thresholds and retrieve the fill-level for each channel via the Avalon® -MM control and fill-level interfaces respectively. Subsequent sections describe the registers accessible via each interface.

Control Register Interface

Table 6.  Control Interface Register Map
Byte Offset Name Access Reset Value Description
0 ALMOST_FULL_THRESHOLD RW 0 Primary almost-full threshold. The bit Almost_full_data[0] on the Avalon® -ST almost-full status interface is set to 1 when the FIFO level is equal to or greater than this threshold.
4 ALMOST_EMPTY_THRESHOLD RW 0 Primary almost-empty threshold. The bit Almost_empty_data[0] on the Avalon® -ST almost-empty status interface is set to 1 when the FIFO level is equal to or less than this threshold.
8 ALMOST_FULL2_THRESHOLD RW 0 Secondary almost-full threshold. The bit Almost_full_data[1] on the Avalon® -ST almost-full status interface is set to 1 when the FIFO level is equal to or greater than this threshold.
12 ALMOST_EMPTY2_THRESHOLD RW 0 Secondary almost-empty threshold. The bit Almost_empty_data[1] on the Avalon® -ST almost-empty status interface is set to 1 when the FIFO level is equal to or less than this threshold.
Base + 8 Almost_Empty_Threshold RW   The value of the primary almost-empty threshold. The bit Almost_empty_data[0] on the Avalon® -ST almost-empty status interface is set to 1 when the FIFO level is less than or equal to this threshold.
Base + 12 Almost_Empty2_Threshold RW   The value of the secondary almost-empty threshold. The bit Almost_empty_data[1] on the Avalon® -ST almost-empty status interface is set to 1 when the FIFO level is less than or equal to this threshold.

Fill-Level Register Interface

The table below shows the register map for the fill-level interface.

Table 7.  Fill-level Interface Register Map
Byte Offset Name Access Reset Value Description
0 fill_level_0 RO 0 Fill level for each channel. Each register is defined for each channel. For example, if the core is configured to support four channel, four fill-level registers are defined.
4 fill_level_1 RO 0
8 fill_level_2 RO 0
(n*4) fill_level_n RO 0