AN 775: Generating Initial I/O Timing Data: for Intel FPGAs

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ID 683103
Date 12/08/2019
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Document Table of Contents
Document Table of Contents x
1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs
1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs x
1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device 1.2. Step 2: Define I/O Standard and Pin Locations 1.3. Step 3: Specify Device Operating Conditions 1.4. Step 4: View I/O Timing in Datasheet Report 1.5. Scripted I/O Timing Data Generation 1.6. AN 775: Generating Initial I/O Timing Data Document Revision History
1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs

1.4. Step 4: View I/O Timing in Datasheet Report

Generate the Datasheet Report in the Timing Analyzer to view the timing parameter values.
  1. In the Timing Analyzer, click Reports > Datasheet > Report Datasheet.
  2. Click OK.
    Figure 7.  Datasheet Report in Timing Analyzer
    The Setup Times, Hold Times, and Clock to Output Times reports appear under the Datasheet Report folder in the Report pane.
  3. Click each report to view the Rise and Fall parameter values.
  4. For a conservative timing approach, specify the maximum absolute value.

Determining I/O Timing Parameters from the Datasheet Report

In the following example Setup Times report, the fall time is greater than the rise time, therefore tSU=tfall .

Figure 8. Setup Times Report

In the following example Hold Times report, the absolute value of the fall time is greater than the absolute value of the rise time, therefore tH=tfall .

Figure 9. Hold Times Report

In the following example Clock to Output Times report, the absolute value of the fall time is greater than the absolute value of the rise time, therefore tCO=tfall .

Figure 10. Clock to Output Times Report
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