AN 775: Generating Initial I/O Timing Data: for Intel FPGAs

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ID 683103
Date 12/08/2019
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1.3. Step 3: Specify Device Operating Conditions

Follow these steps to update the timing netlist and set operating conditions for timing analysis following full compilation:
  1. Click Tools > Timing Analyzer.
  2. In the Task pane, double-click Update Timing Netlist. The timing netlist updates with full compilation timing information that accounts for the pin constraints you make.
    Figure 5. Task Pane in the Timing Analyzer
  3. Under Set Operating Conditions, select one of the available timing models, such as Slow vid3 100C Model or Fast vid3 100C Model.
    Figure 6. Set Operating Conditions in the Timing Analyzer
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