AN 775: Generating Initial I/O Timing Data: for Intel FPGAs
ID
683103
Date
12/08/2019
Public
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1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device
1.2. Step 2: Define I/O Standard and Pin Locations
1.3. Step 3: Specify Device Operating Conditions
1.4. Step 4: View I/O Timing in Datasheet Report
1.5. Scripted I/O Timing Data Generation
1.6. AN 775: Generating Initial I/O Timing Data Document Revision History
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1.2. Step 2: Define I/O Standard and Pin Locations
The specific pin locations and I/O standard you assign to the device pins impacts the timing parameter values. Follow these steps to assign the pin I/O standard and location constraints:
- Click Assignments > Pin Planner.
- Assign pin location and I/O standard constraints according to your design specifications. Enter the Node Name, Direction, Location, and I/O Standard values for the pins in the design in the All Pins spreadsheet. Alternatively, drag node names into the Pin Planner package view.
Figure 4. Pin Locations and I/O Standards Assignments in Pin Planner
- To compile the design, click Processing > Start Compilation. The Compiler generates I/O timing information during full compilation.