1. MAX® 10 External Memory Interface Overview
2. MAX® 10 External Memory Interface Architecture and Features
3. MAX® 10 External Memory Interface Design Considerations
4. MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for MAX® 10 Devices
6. MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the MAX® 10 External Memory Interface User Guide
2.1. MAX® 10 I/O Banks for External Memory Interface
2.2. MAX® 10 DQ/DQS Groups
2.3. MAX® 10 External Memory Interfaces Maximum Width
2.4. MAX® 10 Memory Controller
2.5. MAX® 10 External Memory Read Datapath
2.6. MAX® 10 External Memory Write Datapath
2.7. MAX® 10 Address/Command Path
2.8. MAX® 10 PHY Clock (PHYCLK) Network
2.9. Phase Detector for VT Tracking
2.10. On-Chip Termination
2.11. Phase-Locked Loop
2.12. MAX® 10 Low Power Feature
3.1.1.1.1. MAX® 10 I/O Bank DQ/DQS Support for DDR2/DDR3
For DDR2/DDR3 SDRAM, I/O banks 5 and 6 in MAX® 10 devices can support DQ and DQS signals with DQ-bus widths of 8, 16 and 24 bits.
- For DDR2 and DDR3 SDRAM interfaces, the devices use ×8 mode DQS group regardless of the interface width.
- If you need to support wider interfaces, use multiple ×8 DQ groups.
- You can use any unused DQ pins as regular user I/O pins if they are not used as memory interface signals.
- The x24 interface is implemented through x16 + ECC.
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