1. MAX® 10 External Memory Interface Overview
2. MAX® 10 External Memory Interface Architecture and Features
3. MAX® 10 External Memory Interface Design Considerations
4. MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for MAX® 10 Devices
6. MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the MAX® 10 External Memory Interface User Guide
2.1. MAX® 10 I/O Banks for External Memory Interface
2.2. MAX® 10 DQ/DQS Groups
2.3. MAX® 10 External Memory Interfaces Maximum Width
2.4. MAX® 10 Memory Controller
2.5. MAX® 10 External Memory Read Datapath
2.6. MAX® 10 External Memory Write Datapath
2.7. MAX® 10 Address/Command Path
2.8. MAX® 10 PHY Clock (PHYCLK) Network
2.9. Phase Detector for VT Tracking
2.10. On-Chip Termination
2.11. Phase-Locked Loop
2.12. MAX® 10 Low Power Feature
3.5. Guidelines: Reading the MAX® 10 Pin-Out Files
For the maximum number of DQ pins and the exact number per group for a particular MAX® 10 device, refer to the relevant device pin-out files.
In the pin-out files, the DQS and DQSn pins denote the differential data strobe/clock pin pairs. The DQS and DQSn pins are listed in the MAX® 10 pin-out files as DQSXR and DQSnXR:
- X indicates the DQ/DQS grouping number.
- R indicates the location of the group which is always on the right side of the device.