Intel® Quartus® Prime Timing Analyzer Cookbook

ID 683081
Date 11/12/2018

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Tri-State Outputs

Tri-state outputs allow either a valid data signal or a high impedance signal to be driven out of an output or I/O port. The timing of either signal is important in the overall system timing of the design.

The timing constraints for tri-state outputs are identical to regular output ports.

Figure 11. Typical Output Fed by a Tri-State Buffer

Tri-State Output Port Constraints

# Base clock
create_clock [get_ports {clk}] \
        -name {clk} \
        -period 10.0 \
        -waveform {0.0 5.0}
# Virtual clock for the output port
create_clock  \
        -name {clk_virt} \
        -period 10.0 \
        -waveform {0.0 5.0}
# Output constraints
set_output_delay 2.0 \
        -max \
        -clock [get_clocks {clk_virt}] \
        [get_ports {tri_out}]
set_output_delay 1.0 \
        -min \
        -clock [get_clocks {clk_virt}] \
        [get_ports {tri_out}]

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