Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 11/12/2018
Public

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Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History

Document Version Intel® Quartus® Prime Version Changes
2018.11.12 17.1.0 Corrected error in "Simple Register-to-Register Design with Primary and Secondary Clocks" diagram.
2017.11.21 17.1.0 Updated JTAG Signal Constratints sample code to include option to reset device JTAG controller asynchronously.
2017.11.02 17.1.0 Applied Intel® rebranding.
2016.10.15 16.1.0 Updated the Multicycle Exceptions topic.
2016.02.15 16.0.0
  • Updated the JTAG Signals SDC example
  • Added a section on Unateness of the OE in a packed FF
  • Made corrections to the Clock Enable Multicycle topic.
  • Corrected errors in example scripts and artwork.
2011.01.15 11.0.0
  • Added new sections Toggle Register Generated Clock and Tri-State Outputs.
  • Minor text edits.
2010.03.15 10.0.0 Corrected errors in example script.
2008.08.15 8.1.0 Initial release of document.
Level Two Title