F-Tile Interlaken Intel® FPGA IP Design Example User Guide

ID 683069
Date 3/28/2022

A newer version of this document is available. Customers should click here to go to the newest version.

2.5. Reset

In the F-Tile Interlaken Intel® FPGA IP core, you initiate the reset (reset_n=0) and hold until the IP core returns a reset acknowledge (reset_ack_n=0). After the reset is removed (reset_n=1), the reset acknowledge returns to its initial state (reset_ack_n=1). In the design example, a rst_ack_sticky register holds the reset acknowledge assertion and then triggers the removal of the reset (reset_n=1). You can use alternative methods that fit your design needs.
Important: In any scenario where the internal serial loopback is required, you must release TX and RX of the F-tile separately in a specific order. Refer to the system console script for more information.
Figure 7. Reset Sequence in NRZ Mode
Figure 8. Reset Sequence in PAM4 Mode