F-Tile Interlaken Intel® FPGA IP Design Example User Guide

ID 683069
Date 3/28/2022

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1.5. Compiling and Configuring the Hardware Design Example

  1. Ensure the example design generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_installation_dir>/example_design.qpf>.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a .sof file is available in your specified directory. Follow these steps to program the hardware example design on the Intel® Agilex™ device with F-tile:
    1. Connect the Development Kit to the host computer.
    2. Launch the Clock Control application, which is part of the development kit. Set new frequencies for the design example as following:
      • For NRZ mode:
        • Si5391 (U18), OUT0: Set to the value of pll_ref_clk 2 per your design requirement.
      • For PAM mode:
        • Si5391 (U45), OUT1: Set to the value of pll_ref_clk 2 per your design requirement.
        • Si5391 (U19), OUT1: Set to the value of mac_pll_ref_clk 2 per your design requirement.
    3. Click Tools > Programmer > Hardware Setup.
    4. Select a programming device. Add the Intel® Agilex™ I-Series Transceiver-SoC Development Kit.
    5. Ensure that Mode is set to JTAG.
    6. Select the Intel® Agilex™ I-Series device and click Add Device. The programmer displays a diagram of the connections between the devices on your board.
    7. Check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.
2 The Clock Control GUI application cannot drive all the frequencies.