F-Tile Interlaken Intel® FPGA IP Design Example User Guide

Download PDF
ID 683069
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example 1.6. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Design Example Flow 2.3. Interface Signals 2.4. Register Map 2.5. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

1.6. Testing the Hardware Design Example

After you compile the F-tile Interlaken Intel® FPGA IP design example and configure your device, you can use the System Console to program the IP core and its registers.

Follow these steps to bring up the System Console and test the hardware design example:

  1. In the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
  2. Change to the <design_example_installation_dir>example_design/hwtest directory.
  3. To open a connection to the JTAG master, type the following command: 
    source sysconsole_testbench.tcl
  4. You can turn on internal serial loopback mode with the following design example commands:
    1. stat: Prints general status info.
    2. sys_reset: Resets the system.
    3. loop_on_cpi: Turns on internal serial loopback.
      Note: Default is external loopback mode.
    4. run_example_design: Runs the design example.
  5. You can program the IP core with the following additional design example commands:
    1. gen_on: Enables the packet generator.
    2. gen_off: Disables the packet generator.
    3. sys_reset: System reset.
    4. clear_err: Clears all the CSR sticky error bits.
    5. clear_err_crc: Clears the Design Example CRC error flags.
    6. set_burst_size <burst_size>: Sets burst size in bytes. Acceptable values are 128, 256, or 512.
    7. get_burst_size: Prints burst size information.
    The successful test prints HW_TEST:PASS message. Below is the passing criteria for a test run:
    • No errors for CRC32, CRC24, and checker.
    • Transmitted SOPs and EOPs should match with the received SOPs and EOPs.
    The following sample output illustrates a successful test run in Interlaken mode: 
    __________________________________________________________
	 INFO: INFO: Stop generating packtes
__________________________________________________________

    ==== STATUS REPORT ====
    TX KHz         : 366210
    RX KHz         : 366210
    Freq locks     : 0x000fff
    TX PLL lock    : 0x000001
    Align          : 0x00d10f
    Rx LOA         : 0x000000
    Tx LOA         : 0x000000
    word lock      : 0x000fff
    sync lock      : 0x000fff
    CRC32 errors   : 0
    CRC24 errors   : 0
    Checker errors : 0
    FIFO err flags : 0x000000
    SOPs transmitted   : 4249134583
    EOPs transmitted   : 4249134583
    SOPs received      : 4249134583
    EOPs received      : 4249134583
    ECC corrected      : 3
    ECC error          : 15

    Elapsed 161 sec since powerup

HW_TEST : PASS
    The following sample output illustrates a successful test run in Interlaken Look-aside mode: 
    __________________________________________________________
	 INFO: INFO: Stop generating packtes
__________________________________________________________

    ==== STATUS REPORT ====
    TX KHz         : 195312
    RX KHz         : 195312
    Freq locks     : 0x000fff
    TX PLL lock    : 0x000001
    Align          : 0x00d10f
    Rx LOA         : 0x000000
    Tx LOA         : 0x000000
    word lock      : 0x000fff
    sync lock      : 0x000fff
    CRC32 errors   : 0
    CRC24 errors   : 0
    Checker errors : 0
    FIFO err flags : 0x000000
    SOPs transmitted   : 3314317815
    EOPs transmitted   : 3314317815
    SOPs received      : 3314317815
    EOPs received      : 3314317815

    Elapsed 163 sec since powerup

HW_TEST : PASS
Level Two Title