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2.2. Design Example Flow
The F-Tile Interlaken Intel® FPGA IP hardware design example completes the following steps:
- Reset the the F-tile Interlaken Intel® FPGA IP and F-Tile.
- Release the reset on Interlaken IP (system reset) and F-tile TX (tile_tx_rst_n).
- Configures the F-tile Interlaken Intel® FPGA IP in the internal loopback mode.
- Release the reset of F-tile RX (tile_rx_rst_n).
- Sends a stream of Interlaken packets with predefined data in the payload to the TX user data transfer interface of the IP core.
- Checks the received packets and reports the status. The packet checker included in the hardware design example provides the following basic packet checking capabilities:
- Check that the transmitted packet sequence is correct.
- Checks that the received data matches the expected values by ensuring both the start of packet (SOP) and end of packet (EOP) counts align while data is being transmitted and received.
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