1.6. Test Result Comments
In each test case, the JESD204B receiver IP core successfully initializes from CGS phase, ILA phase, and until user data phase.
No data integrity issue is observed by the PRBS and Ramp checker for all JESD configurations.
Note: Deterministic latency between AD9213 and Intel® Stratix® 10 FPGA is not characterized.
Pattern Checker Modifications to Match AD9213 Data Formats
We have hardcoded the csr_m and csr_s values in the pattern generator and checker to match the ADC AD9213 data format. The hardcoded values are as follows:
| Test Modes | Hardcoded Values |
|---|---|
| LMF_212_S_2 | M = 2 & S = 1 |
| LMF_411_S_2 | M = 2 & S = 1 |
| LMF_412_S_4 | M = 4 & S = 1 |
| LMF_811_S_4 | M = 4 & S = 1 |
| LMF_812_S_8 | M = 8 & S = 1 |
| LMF_422_S_2 | M = 4 & S = 1 |
| LMF_821_S_2 | M = 4 & S = 1 |
| LMF_822_S_4 | M = 8 & S = 1 |
| LMF_1612_S_16 and LMF_1622_S_8 | M = 16 & S = 1 |
| LMF_1611_S_8 and LMF_1621_S_4 | M = 8 & S = 1 |
Additional JESD modes supported by ADC
The modes enlisted here have not been validated in this interoperability report, but they are supported by the ADC. These have been tabulated here for reference.
| L M F | S | N | N' | Comments |
|---|---|---|---|---|
| 3 1 1 | 2 | 12 | 12 | N’=12 configuration is not supported by transport layer of Intel example design. |
| 6 1 1 | 4 | 12 | 12 | |
| 12 1 1 | 8 | 12 | 12 | |
| 3 2 1 | 1 | 12 | 12 | |
| 6 2 1 | 2 | 12 | 12 | |
| 12 2 1 | 4 | 12 | 12 | |
| 1 1 1 | 1 | 8 | 8 | N’=8 configuration is not supported by transport layer of Intel example design |
| 1 1 2 | 2 | 8 | 8 | |
| 2 1 1 | 2 | 8 | 8 | |
| 2 1 2 | 4 | 8 | 8 | |
| 2 1 4 | 8 | 8 | 8 | |
| 4 1 1 | 4 | 8 | 8 | |
| 4 1 2 | 8 | 8 | 8 | |
| 8 1 1 | 8 | 8 | 8 | |
| 8 1 2 | 16 | 8 | 8 | |
| 1 2 2 | 1 | 8 | 8 | |
| 2 2 1 | 1 | 8 | 8 | |
| 2 2 2 | 2 | 8 | 8 | |
| 4 2 1 | 2 | 8 | 8 | |
| 4 2 2 | 4 | 8 | 8 | |
| 4 2 4 | 8 | 8 | 8 | |
| 8 2 1 | 4 | 8 | 8 | |
| 8 2 2 | 8 | 8 | 8 | |
| 8 2 4 | 16 | 8 | 8 |