AN 905: JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel Stratix® 10 Devices

ID 683056
Date 12/16/2019

1.3.1. Receiver Data Link Layer

This test area covers the test cases for code group synchronization (CGS) and initial lane alignment (ILA) sequence.

On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The Signal Tap logic analyzer monitors the receiver data link layer operation.