AN 905: JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel Stratix® 10 Devices

ID 683056
Date 12/16/2019
Public

1.8. Appendix

Device Used and Quartus Tool Version

The Intel® Stratix® 10 1SX280LU2F50E2VGS3 device (transceiver speed grade -2 device) is used.

The Intel® Quartus® Prime Pro Edition software version 18.0 Build 219 is used for compilation of designs.

Timing Closure Details

Synthesis/Fitter Settings:

The following Analysis/Fitter settings were added to the Quartus Settings File (.qsf) to close the timing requirements for some parameter configuration modes, where the Number of Lanes = 8.

Compiler Setting Value Used Default Value
Optimization Technique Speed Balanced
Physical Synthesis ON OFF
Router Timing Optimization Level Maximum Normal
Auto Packed Registers Normal Auto
Restructure Multipliers OFF Auto