Interlaken (2nd Generation) Intel® FPGA IP Release Notes

Download PDF
ID 683052
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Interlaken (2nd Generation) Intel® FPGA IP FPGA IP Release Notes
1. Interlaken (2nd Generation) Intel® FPGA IP FPGA IP Release Notes x
1.1. Interlaken (2nd Generation) Intel® FPGA IP v21.1.3 1.2. Interlaken (2nd Generation) Intel® FPGA IP v20.0.0 1.3. Interlaken (2nd Generation) Intel® FPGA IP v19.3.0 1.4. Interlaken (2nd Generation) Intel® FPGA IP v19.2.1 1.5. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP v18.1 Update 1 1.6. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP v18.1 1.7. Interlaken (2nd Generation) Intel® FPGA IP v18.0.1 1.8. Interlaken (2nd Generation) Intel® FPGA IP v18.0 1.9. Interlaken IP Core (2nd Generation) v17.1 1.10. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
1. Interlaken (2nd Generation) Intel® FPGA IP FPGA IP Release Notes

1.3. Interlaken (2nd Generation) Intel® FPGA IP v19.3.0

Table 3.  v19.3.0 2020.06.22
Intel® Quartus® Prime Version Description Impact
19.3.0 The IP now supports Interlaken Look-aside feature. —
Added new Enable Interlaken Look-aside mode parameter in the IP parameter editor. You can configure the IP in Interlaken Look-aside mode.
Transfer mode selection parameter is removed from the current version of the Intel® Quartus® Prime software. —
Added 12.5 Gbps data rate support for number of lanes 10 in H-tile and E-tile (NRZ mode) IP core variations. —
Removed the following signals from the IP:
  • rx_pma_data
  • tx_pma_data
  • itx_hungry
  • itx_hungry
—
Added following new signals:
  • sop_cntr_inc1
  • eop_cntr_inc1
  • rx_xcoder_uncor_feccw
  • itx_ch0_xon
  • irx_ch0_xon
  • itx_ch1_xon
  • irx_ch1_xon
  • itx_valid
  • irx_valid
  • itx_idle
  • irx_idle
  • itx_ctrl
  • itx_credit
  • irx_credit
—
Removed following two offsets from register map:
  • 16'h40- TX_READY_XCVR
  • 16'h41- RX_READY_XCVR
—
Hardware testing of the design example is now available for Intel Agilex® 7 devices. You can test the design example on Intel Agilex® 7 F-series Transceiver-SoC Development Kit.
You can change the data rate and transceiver reference clock frequency to slightly different values for your Interlaken (2nd Generation) IP instance that targets Intel® Stratix® 10 H-tile or E-tile device. Refer to this KDB for information on how to change the data rate. You can customize the data rates depending on the tiles.
Level Two Title