Interlaken (2nd Generation) Intel® FPGA IP Release Notes

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ID 683052
Date 12/04/2023
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1. Interlaken (2nd Generation) Intel® FPGA IP FPGA IP Release Notes
1. Interlaken (2nd Generation) Intel® FPGA IP FPGA IP Release Notes x
1.1. Interlaken (2nd Generation) Intel® FPGA IP v21.1.3 1.2. Interlaken (2nd Generation) Intel® FPGA IP v20.0.0 1.3. Interlaken (2nd Generation) Intel® FPGA IP v19.3.0 1.4. Interlaken (2nd Generation) Intel® FPGA IP v19.2.1 1.5. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP v18.1 Update 1 1.6. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP v18.1 1.7. Interlaken (2nd Generation) Intel® FPGA IP v18.0.1 1.8. Interlaken (2nd Generation) Intel® FPGA IP v18.0 1.9. Interlaken IP Core (2nd Generation) v17.1 1.10. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
1. Interlaken (2nd Generation) Intel® FPGA IP FPGA IP Release Notes

1.5. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP v18.1 Update 1

Table 5.  Version 18.1 Update 1 2019.03.15
Description Impact
Added multi-segment mode support. —
Added Number of Segments parameter. —
  • Added support for lane and data rate combinations as follows:
    • For Intel® Stratix® 10 L-tile devices:
      • 4 lanes with 12.5/25.3/25.8 Gbps lane rates
      • 8 lanes with 12.5 Gbps lane rates
    • For Intel® Stratix® 10 H-tile devices:
      • 4 lanes with 12.5/25.3/25.8 Gbps lane rates
      • 8 lanes with 12.5/25.3/25.8 Gbps lane rates
      • 10 lanes with 25.3/25.8 Gbps lane rates
    • For Intel® Stratix® 10 E-tile (NRZ) devices:
      • 4 lanes with 6.25/12.5/25.3/25.8 Gbps lane rates
      • 8 lanes with 12.5/25.3/25.8 Gbps lane rates
      • 10 lanes with 25.3/25.8 Gbps lane rates
      • 12 lanes with 10.3125 Gbps lane rate
—
  • Added the following new transmit user interface signals:
    • itx_eob1
    • itx_eopbits1
    • itx_chan1
—
  • Added the following new receiver user interface signals:

    • irx_eob1

    • irx_eopbits1

    • irx_chan1

    • irx_err1

    • irx_err

 —
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