1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices 4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives 5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameters 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
184.108.40.206. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
220.127.116.11. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0)
After generating the design, you need to edit the HDCP key memory files to include your production keys.
To include the production keys, follow these steps.
- Locate the following key memory files in the <project directory>/rtl/hdcp/ directory:
- Open the hdcp2x_rx_kmem.v file and locate the predefined facsimile key R1 for Receiver Public Certificate and RX Private Key and Global Constant as shown in the examples below.
Figure 16. Wire Array of Facsimile Key R1 for Receiver Public CertificateFigure 17. Wire Array of Facsimile Key R1 for RX Private Key and Global Constant
- Locate the placeholder for the production keys and replace with your own production keys in their respective wire array in big endian format.
Figure 18. Wire Array of HDCP Production Keys (Placeholder)
- Repeat Step 3 for all other key memory files. When you have finished including your production keys in all the key memory files, ensure that the USE_FACSIMILE parameter is set to 0 at the design example top level file (a10_dp_demo.v ).
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