DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

ID 683050
Date 2/01/2023

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2.3. Enabling Adaptive Sync Support

To enable support for the Adaptive Sync feature in the design examples without PCR, you need to edit the MSA_TIMING_PAR_IGNORED bit of the DPCD 00007h register and the MSA_TIMING_PAR_IGNORE_EN bit of the DPCD 00107h register in the rx_utils.c file in the software folder.
Note: The Adaptive Sync feature is applicable only when you turn on the Enable GPU control parameter.
To edit the bits:
  1. Locate data[7] = 0x80; // DPCD_ADDR_DOWN_STREAM_PORT_COUNT.
  2. Change 0x80 to 0xC0.
  3. Locate data[7] = 0x00; // DPCD_ADDR_DOWNSPREAD_CTRL
  4. Change 0x00 to 0x80.
  5. Regenerate the ELF file, refer to Regenerating ELF File.
  6. After programming the SOF file into the FPGA, program the updated ELF file into the FPGA.